Low Power SRAM Design using Hierarchical Divided Bit-Line Approach

Authors:
Ashish Karandikar
Affiliations:
-
Venue:
ICCD '98 Proceedings of the International Conference on Computer Design
Year:
1998

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Abstract

This Paper presents a novel hierarchical divided bit-line approach for reducing active power in SRAMs by reducing bit-line capacitance. Two or more 6T SRAM cells are combined together to divide the bit-line into several sub bit-lines. These sub bit-lines are again combined to form two or more levels of hierarchy. This division of bit-line into hierarchical sub bit-lines results in reduction of bit-line capacitance, which reduces active power and access time. Optimum values for number of levels of hierarchy and number of blocks combined at each level have been derived. Experimental results show that observed parameters and estimated ones follow the same trend. It is shown that the reduction in bit-line capacitance reduces active power consumption by 50-60% and also reduces access time by about $20\% $ at the expense of approximately 5% increase in the number of transistors. This approach is further extended by incorporating the controlled voltage swing on bit-lines. This extension reduces the power consumption by another 20-30%.