Algorithmic graph theory
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Improved Yield Models for Fault-Tolerant Memory Chips
IEEE Transactions on Computers
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Novel Built-In Self-Repair Approach for Embedded RAMs
Journal of Electronic Testing: Theory and Applications
Address and Data Scrambling: Causes and Impact on Memory Tests
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Low Power SRAM Design using Hierarchical Divided Bit-Line Approach
ICCD '98 Proceedings of the International Conference on Computer Design
Novel Fault-Tolerant Techniques for High Capacity RAMs
PRDC '01 Proceedings of the 2001 Pacific Rim International Symposium on Dependable Computing
Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs
MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
A Fault-Driven, Comprehensive Redundancy Algorithm
IEEE Design & Test
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Journal of Electronic Testing: Theory and Applications
Gating transistor power saving technique for power optimized code book SRAM
Proceedings of the International Conference on Advances in Computing, Communication and Control
Modified essential spare pivoting algorithm for embedded memories with global block-based redundancy
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
On topology reconfiguration for defect-tolerant NoC-based homogeneous manycore systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient BISR techniques for embedded memories considering cluster faults
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
EOF: efficient built-in redundancy analysis methodology with optimal repair rate
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Matrix codes for reliable and cost efficient memory chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mathematical yield estimation for two-dimensional-redundancy memory arrays
Proceedings of the International Conference on Computer-Aided Design
Efficient memory repair using cache-based redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
A novel redundant mechanism is proposed for embedded memories in this paper. Redundant rows and columns are added into the memory array as in the conventional approaches. However, the redundant rows and columns are divided into row blocks and column blocks, respectively. The reconfiguration is performed at the row (column) block level instead of the conventional row (column) level. Based on the proposed redundant mechanism, we first show that the complexity of the redundancy allocation problem is NP-complete. Thereafter, an extended local repair-most (ELRM) algorithm suitable for built-in implementation is proposed. The complexity of the ELRM algorithm is O(N), where N denotes the number of memory cells. According to the simulation results, the hardware overhead for implementing this algorithm is below 0.17% for a 1024 × 2048-b SRAM. Due to the efficient usage of the redundant elements, the manufacturing yield, repair rate, and reliability can be improved significantly.