Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Content-addressable memory core cells: a survey
Integration, the VLSI Journal
On programmable memory built-in self test architectures
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
Test and repair of large embedded DRAMs. 2
Proceedings of the IEEE International Test Conference 2001
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Memory built-in self-repair using redundant words
Proceedings of the IEEE International Test Conference 2001
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
MTDT '99 Proceedings of the 1999 IEEE International Workshop on Memory Technology, Design, and Testing
Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, a novel built-in self-repair approach, block-level reconfiguration architecture, is proposed. Our approach is based on the concept of divided word line (DWL) for high-capacity memories, including SRAMs and DRAMs. This concept is widely used in low-power memory designs. However, the characteristics of divided word line memories have not been used for fault-tolerant applications. Therefore, we propose the block_repair fault-tolerant architecture based on the structure of DWL for high-capacity memories. The redundant rows of a memory array are divided into blocks and reconfiguration is performed at the block level instead of the traditional row level. Our fault-tolerant architecture can improve the yield for memory fabrication significantly. Moreover, the characteristics of low power and fast access time of DWL memories are also preserved. The reconfiguration mechanism of our block_repair architecture requires negligible hardware overhead. According to experimental results, the hardware overheads are less than 0.73% and 0.48% for 256-Kbit SRAMs and 8-Mbit DRAMs, respectively. The repair rate of our approach with previous memory repair algorithms is compared. It is found that block_repair approach improves repair rate significantly. The yield improvement over traditional row-based approaches is also analyzed. Simulated results show that the present approach can significantly improve fabrication yield.