Testing and testable design of high-density random-access memories
Testing and testable design of high-density random-access memories
Defect oriented testing for CMOS analog and digital circuits
Defect oriented testing for CMOS analog and digital circuits
On programmable memory built-in self test architectures
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Design of Cache Test Hardware on the HP PA8500
Proceedings of the IEEE International Test Conference
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
A Fault-Driven, Comprehensive Redundancy Algorithm
IEEE Design & Test
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
A Novel Built-In Self-Repair Approach for Embedded RAMs
Journal of Electronic Testing: Theory and Applications
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Memory Built-In Self-Repair using redundant words
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A data acquisition methodology for on-chip repair of embedded memories
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Journal of Electronic Testing: Theory and Applications
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a built-in self-test (BIST) scheme,which consists of a flexible pattern generator and a practicalon-macro two-dimensional redundancy analyzer, forGHz embedded SRAMs. In order to meet the system requirementsand to detect a wide variety of faults or performancedegradation resulting from recent technologyadvances, the microcode-based pattern generator cangenerate flexible patterns. A practical new repair algorithmfor the Finite State Machine (FSM)-based on-macroredundancy analyzer is also presented. It can beimplemented with simple hardware and can show fairlygood performance compared with conventional software-based algorithms.