Simulation-based test algorithm generation and port scheduling for multi-port memories
Proceedings of the 38th annual Design Automation Conference
Design and Test of Large Embedded Memories: An Overview
IEEE Design & Test
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Memory built-in self-repair using redundant words
Proceedings of the IEEE International Test Conference 2001
Embedded-Memory Test and Repair: Infrastructure IP for SoC Yield
IEEE Design & Test
Address and Data Scrambling: Causes and Impact on Memory Tests
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
Detection of Inter-Port Faults in Multi-Port Static RAMs
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
A Built-In Self-Repair Analyzer (CRESTA) for embedded DRAMs
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Embedded Memory Test and Repair: Infrastructure IP for SOC Yield
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Realistic Fault Models and Test Procedures for Multi-Port SRAMs
MTDT '01 Proceedings of the International Workshop on Memory Technology, Design, and Testing (MTDT'01)
Built-In Self-Test for GHz Embbedded SRAMS Using Flexible Pattern Generator And New Repair Algorithm
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Algorithm for Row-Column Self-Repair of RAMs and Its Implementation in the Alpha 21264
ITC '99 Proceedings of the 1999 IEEE International Test Conference
At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Dynamic Data-bit Memory Built-In Self- Repair
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
ETS '07 Proceedings of the 12th IEEE European Test Symposium
A Built-In Self-Repair Scheme for Multiport RAMs
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Efficient Spare Allocation for Reconfigurable Arrays
IEEE Design & Test
Raisin: Redundancy Analysis Algorithm Simulation
IEEE Design & Test
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Journal of Electronic Testing: Theory and Applications
ProTaR: an infrastructure IP for repairing RAMs in system-on-chips
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ReBISR: a reconfigurable built-in self-repair scheme for random access memories in SOCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient built-in redundancy analysis for embedded memories with 2-d redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A built-in self-repair design for RAMs with 2-D redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Built-in self-repair (BISR) techniques are widely used to enhance the yield of embedded random access memories (RAMs). Fault-location ability of test algorithms executed by a BISR circuit has heavy impact on the repair efficiency of the BISR circuit. This paper proposes a defect-aware BISR (DABISR) scheme for single-port RAMs (SPRAMs) and multi-port RAMs (MPRAMs) in system chips. Multiple RAMs can share a DABISR such that the area cost of DABISR is drastically reduced. We also present two defect-location algorithms (DLAs) for identification of bridge defects between word-lines and bit-lines of MPRAMs. The DABISR can perform DLAs to locate bridge defects such that it can provide high repair efficiency. For example, simulation results show that if a faulty two-port RAM has 20% inter-port faults, the DLAs can help to gain 8.4-14.4% increase of repair rate for different redundancy configurations. In comparison with an existing shared BISR scheme, however, the DABISR only incurs about 0.34% additional area overhead to support the function of DLAs.