Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing complex couplings in multiport memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error catch and analysis for semiconductor memories using march tests
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
RAMSES: A Fast Memory Fault Simulator
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Built-In Self-Test for Multi-Port RAMs
ATS '97 Proceedings of the 6th Asian Test Symposium
An efficient test method for embedded multi-port RAM with BIST circuitry
MTDT '95 Proceedings of the 1995 IEEE International Workshop on Memory Technology, Design and Testing
18.2 Fault Models and Tests for Two-Port Memories
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Simulation-Based Test Algorithm Generation for Random Access Memories
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Detection of Inter-Port Faults in Multi-Port Static RAMs
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
DABISR: a defect-aware built-in self-repair scheme for single/multi-port RAMs in SoCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special section on the ACM IEEE international conference on formal methods and models for codesign (MEMOCODE) 2009
| Hi-index | 0.00 |
The paper presents a simulation-based test algorithm generation and test scheduling methodology for multi-port memories. The purpose is to minimize the testing time while keeping the test algorithm in a simple and regular format for easy test generation, fault diagnosis, and built-in self-test (BIST) circuit implementation. Conventional functional fault models are used to generate tests covering most defects. In addition, multi-port specific defects are covered using structural fault models. Port-scheduling is introduced to take advantage of the inherent parallelism among different ports. Experimental results for commonly used multi-port memories, including dual-port, four-port, and $n$-read-1-write memories, have been obtained, showing that efficient test algorithms can be generated and scheduled to meet different test bandwidth constraints. Moreover, memories with more ports benefit more with respect to testing time.