Memory fault diagnosis by syndrome compression
Proceedings of the conference on Design, automation and test in Europe
Simulation-based test algorithm generation and port scheduling for multi-port memories
Proceedings of the 38th annual Design Automation Conference
Error catch and analysis for semiconductor memories using march tests
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test
Journal of Electronic Testing: Theory and Applications
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
Journal of Electronic Testing: Theory and Applications
Testing and Diagnosis Methodologies for Embedded Content Addressable Memories
Journal of Electronic Testing: Theory and Applications
A Fast Diagnosis Scheme for Distributed Small Embedded SRAMs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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In this paper, we present a memory fault simulator called the Random Access Memory Simulator for Error Screening (RAMSES). Although it was designed based on some well-known memory fault models, the algorithm that we developed ensures that new fault models can be included easily by adding new fault descriptors instead of modifying the algorithm or program. With RAMSES, the time complexity of memory fault simulation is improved from $O(N^3)$ to $O(N^2)$, where $N$ is the memory capacity in terms of bits. Our approach requires only a small amount of extra memory space. Simulation results by RAMSES show that running the proposed cocktail-March tests can significantly reduce the test time. With the help of RAMSES, an efficient test algorithm called March-CW was developed for word-oriented memories.