Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Content-addressable memory core cells: a survey
Integration, the VLSI Journal
Testing SRAM-Based Content Addressable Memories
IEEE Transactions on Computers
RAMSES: A Fast Memory Fault Simulator
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Testing content-addressable memories using functional fault models and march-like algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Built-in self-repair schemes for flash memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Testing comparison and delay faults of TCAMs with asymmetric cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design techniques and test methodology for low-power TCAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Embedded content addressable memories (CAMs) are important components in many system chips where most CAMs are customized and have wide words. This poses challenges on testing and diagnosis. In this paper two efficient March-like test algorithms are proposed first. In addition to typical RAM faults, they also cover CAM-specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N + W) Compare operations to cover comparison and RAM faults (but does not fully cover the intra-word coupling faults), for an N × W-bit CAM. The second algorithm uses 3N log2 W Write and 2W log2 W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover, it can test the CAM even when its comparison result is observed only by the Hit output or the priority encoder output. We also present the algorithms that can locate the cells with comparison faults. Finally, a CAM BIST design is briefly described.