Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Tutorial on semiconductor memory testing
Journal of Electronic Testing: Theory and Applications - Special issue: on memory testing
Diagnostic testing of embedded memories using BIST
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Memory fault diagnosis by syndrome compression
Proceedings of the conference on Design, automation and test in Europe
Error catch and analysis for semiconductor memories using march tests
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Using March Tests to Test SRAMs
IEEE Design & Test
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
Industrial BIST of Embedded RAMs
IEEE Design & Test
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
RAMSES: A Fast Memory Fault Simulator
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
March-based RAM diagnosis algorithms for stuck-at and coupling faults
Proceedings of the IEEE International Test Conference 2001
An experimental analysis of spot defects in SRAMs: realistic fault models and tests
ATS '00 Proceedings of the 9th Asian Test Symposium
RAM Testing Algorithm for Detection Linked Coupling Faults
EDTC '96 Proceedings of the 1996 European conference on Design and Test
March LA: a test for linked memory faults
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Simulation-Based Test Algorithm Generation for Random Access Memories
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Automatic Generation of Diagnostic March Tests
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
March-Based RAM Diagnosis Algorithms for Stuck-At and Coupling Faults
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Efficient Transparent Test Scheme for Embedded Word-Oriented Memories
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy
Journal of Electronic Testing: Theory and Applications
An Efficient Diagnosis Scheme for RAMs with Simple Functional Faults
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Diagnosis of MRAM write disturbance fault
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we propose a novel built-in self-test (BIST) design for embedded SRAM cores. Our contribution includes a compact and efficient BIST circuit with diagnosis support and an automatic diagnostic system. The diagnosis module of our BIST circuit can capture the error syndromes as well as fault locations for the purposes of repair and fault/failure analysis. In addition, our design provides programmability for custom March algorithms with lower hardware cost. The combination of the on-line programming mode and diagnostic system dramatically reduces the effort in design debugging and yield enhancement. We have designed and implemented test chips with our BIST design. Experimental results show that the area overhead of the proposed BIST design is only 2.4% for a 128 KB SRAM, and 0.65% for a 2 MB one.