Error catch and analysis for semiconductor memories using march tests
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A Built-in Self-Test Scheme with Diagnostics Support for Embedded SRAM
Journal of Electronic Testing: Theory and Applications
Industrial BIST of Embedded RAMs
IEEE Design & Test
A Programmable BIST Core for Embedded DRAM
IEEE Design & Test
BRAINS: A BIST Compiler for Embedded Memories
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
MTDT '03 Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing
Flash Memory Built-In Self-Diagnosis with Test Mode Control
VTS '05 Proceedings of the 23rd IEEE Symposium on VLSI Test
MRAM Defect Analysis and Fault Modeli
ITC '04 Proceedings of the International Test Conference on International Test Conference
MRAM Write Error Categorization with QCKB
MTDT '06 Proceedings of the 2006 IEEE International Workshop on Memory Technology, Design, and Testing
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Write disturbance modeling and testing for MRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The science and technology of magnetoresistive tunneling memory
IEEE Transactions on Nanotechnology
Hi-index | 0.00 |
In this paper, we propose a new test method to detect write disturbance fault (WDF) for magnetic RAM (MRAM). Furthermore, an adaptive diagnosis algorithm (ADA) is also introduced to identify and diagnose the WDF for MRAM. The proposed test method can evaluate process stability and uniformity. We also develop a built-in self-test (BIST) circuit that supports the proposed WDF diagnosis test method. A 1-Mb toggle MRAM prototype chip with the proposed BIST circuit has been designed and fabricated using a special 0.15-µm CMOS technology. The BIST circuit overhead is only about 0.05% with respect to the 1-Mb MRAM. The test time is reduced by about 30% as compared with the test method without using the decision write mechanism. The chip measurement results show the efficiency of our proposed method.