Economic Aspects of Memory Built-in Self-Repair
IEEE Design & Test
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Fast identification of operating current for toggle MRAM by spiral search
Proceedings of the 47th Design Automation Conference
Diagnosis of MRAM write disturbance fault
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Write disturbance modeling and testing for MRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impact of resistive-open defects on the heat current of TAS-MRAM architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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With the advent of system-on-chip (SOC), the demand for embedded memory cores increases rapidly. The Magnetic Random Access Memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM has a high speed and does not need high supply voltage for Read/Write operations, so it has the advantages of RAM and flash memory, making it a potentially good choice for SOC. The testing of MRAM, however, has not been fully investigated. In this work we classify and analyze the MRAM defects and their behavior, and propose its fault models. We have built a SPICE model of MRAM cell and performed defect injection and simulation of a real MRAM circuit. The circuit has been implemented and fabricated with a novel 0.18ìm technology. The simulation results regarding the correlation between the defects and conventional fault models show that most of the defects can be covered by the stuck-at fault model. The test data based on the fabricated chips show that the stuck-at faults do cover most of the defects on the chips. However, from the experiment we also have identified two new faults, i.e., the Multi-Victims fault and Kink fault.