BRAINS: A BIST Compiler for Embedded Memories
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
MRAM Defect Analysis and Fault Modeli
ITC '04 Proceedings of the International Test Conference on International Test Conference
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Write disturbance modeling and testing for MRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Magnetic Random Access Memory (MRAM) is a non-volatile memory which is widely studied for its high speed, high density, small cell size, and almost unlimited endurance. However, for deep-submicron process technologies, significant variation in MRAM cells' operating regions results in write failures in cells and reduces the production yield. Currently, memory designers characterize failed MRAM chips to find a suitable current level for reconfiguring their operating current, which is time-consuming. In this paper, we propose an efficient operating current search method and a built-in circuit for toggle MRAM, which can rapidly find a customized operating current for each MRAM chip. With the built-in circuit, an MRAM chip can dynamically reconfigure its operating current automatically. Production yield and product life-time thus can be increased.