Write disturbance modeling and testing for MRAM

Authors:
Chin-Lung Su;Chih-Wea Tsai;Cheng-Wen Wu;Chien-Chung Hung;Young-Shying Chen;Ding-Yeong Wang;Yuan-Jen Lee;Ming-Jer Kao
Affiliations:
Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;R&D Department, Skymedi Corporation, Hsinchu, Taiwan, R.O.C.;Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan, R.O.C.;Department of Non-Volatile Memory Technology, Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan;Department of Non-Volatile Memory Technology, Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan;Department of Non-Volatile Memory Technology, Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan;Nanoelectronic Device Technology Division, Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan;Department of Non-Volatile Memory Technology, Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2008

Citing 13
Cited 3

Testing semiconductor memories: theory and practice

Testing semiconductor memories: theory and practice
Diagnostic testing of embedded memories using BIST

DATE '00 Proceedings of the conference on Design, automation and test in Europe
Error catch and analysis for semiconductor memories using march tests

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
March-based RAM diagnosis algorithms for stuck-at and coupling faults

Proceedings of the IEEE International Test Conference 2001
Flash Memory Built-In Self-Test Using March-Like Algorithms

DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Testing Flash Memories

VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Diagonal Test and Diagnostic Schemes for Flash Memories

ITC '02 Proceedings of the 2002 IEEE International Test Conference
Flash Memory Disturbances: Modeling and Test

VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics

VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
ITRS Commodity Memory Roadmap

MTDT '03 Proceedings of the 2003 International Workshop on Memory Technology, Design and Testing
Tutorial on Magnetic Tunnel Junction Magnetoresistive Random-Access Memory

MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
MRAM Defect Analysis and Fault Modeli

ITC '04 Proceedings of the International Test Conference on International Test Conference
Fault simulation and test algorithm generation for random access memories

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Energy reduction for STT-RAM using early write termination

Proceedings of the 2009 International Conference on Computer-Aided Design
Fast identification of operating current for toggle MRAM by spiral search

Proceedings of the 47th Design Automation Conference
Diagnosis of MRAM write disturbance fault

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

The magnetic random access memory (MRAM) is considered one of the potential candidates that will replace current on-chip memories (RAM, EEPROM, and flash memory) in the future. The MRAM is fast and does not need a high supply voltage for read/write operations, and is compatible with the CMOS technology. It can also endure almost unlimited read/write cycles. These combined advantages of RAM and flash memory make it a potential choice for SOC. In this paper, we present the write disturbance fault (WDF) model for MRAM, i.e., a fault that affects the data stored in the MRAM cells due to excessive magnetic field during the write operation. We also construct the SPICE macro model for the magnetic tunneling junction (MTJ) device of the toggle MRAM to obtain circuit simulation results. We then present an MRAM fault simulator called RAMSES-M, based on which we derive the shortest test for the proposed WDF model. The test is shown to be better and more robust as compared with the conventional March C- test algorithm. We also present a March 17 N diagnosis algorithm for identifying WDF. A 1 Mb MRAM chip has been designed and fabricated using a CMOS-based 0.18-µm technology. The proposed WDF model is justified by chip measurement results, with the march test results reported. Finally, specific MRAM fault behavior and test issues are discussed.