Techniques for Disturb Fault Collapsing
Journal of Electronic Testing: Theory and Applications
An efficient fault detection algorithm for NAND flash memory
ACM SIGAPP Applied Computing Review
Write disturbance modeling and testing for MRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Embedded flash memory plays an increasingly important role for system-on-chip (SOC), especially for battery-powered devices. Testing and diagnosis of embedded flash memory is becoming one of the key development and production issues for many SOC products. Moreover, high density, high capacity, and the integration of heterogeneous cores in an SOC results in long test time, which in turn lead to high test cost. In this paper we propose a new diagonal test algorithm for flash memory that effectively reduces the test time without sacrificing the fault coverage. Both disturb faults and conventional RAM faults are covered. A diagnostic algorithm is also presented, which can distinguish among all the disturb faults and most of the conventional RAM faults. Finally, a built-in self-diagnosis (BISD) scheme is proposed. The BISD circuit implements our algorithms and user-defined ones, and its area overhead is low, e.g., it contains only about 2,551 gates (2-3%) for a 2Mb flash memory. Thetest time by our diagonal test is reduced by about 42.69% as compared with the best March-like algorithm reported so far.