Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Fault Models and Test Procedures for Flash Memory Disturbances
Journal of Electronic Testing: Theory and Applications
Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs
IEEE Transactions on Computers
Flash Memory Built-In Self-Test Using March-Like Algorithms
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Functional Memory Faults: A Formal Notation and a Taxonomy
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Diagonal Test and Diagnostic Schemes for Flash Memories
ITC '02 Proceedings of the 2002 IEEE International Test Conference
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Fault Collapsing for Flash Memory Disturb Faults
ETS '05 Proceedings of the 10th IEEE European Symposium on Test
Optimizing program disturb fault tests using defect-based testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RFID System On-line Testing Based on the Evaluation of the Tags Read-Error-Rate
Journal of Electronic Testing: Theory and Applications
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Disturb faults are considered one the most important failure modes in non volatile memories. Disturb faults are highly dependant on the core memory cell structure, manufacturing technology, and array organization. In this paper, we analyze the origins of such disturbs and propose a method that uses cell structure and array organization information to identify the relevant disturbs and to create a reduced fault list. To demonstrates its effectiveness, the method was used to create minimized fault lists for NOR and NAND flash memory arrays. Moreover, we show how the reduced fault list developed can be used to devise more efficient test algorithms.