Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing and testable design of high-density random-access memories
Testing and testable design of high-density random-access memories
Designing with Flash Memory
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Flash Memory Disturbances: Modeling and Test
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Electrical Model For Program Disturb Faults in Non-Volatile Memories
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Techniques for Disturb Fault Collapsing
Journal of Electronic Testing: Theory and Applications
An efficient fault detection algorithm for NAND flash memory
ACM SIGAPP Applied Computing Review
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Disturbances are special type of faults that are unique to flash memories. Causes of the disturbances are defects within the insulating layers of the memory element. These defects result in abnormal behavior of a memory cell under specific conditions. This paper describes characteristics of these defects as well as their manifestation as DC-Programming, DC-Erasure, and Drain Disturbance. We develop fault models to capture the behavior of faulty flash memories. We introduce three different fault models based on the underlying defects in a memory cell. These models are: Simple, Exclusive and General Fault model. Further, we develop test algorithms that detect disturbance faults under each of the fault models. The test algorithms reported in this paper for the simple fault model for each type of disturbance require optimal number of program, read, and flash operations; where as the algorithms for the remaining two fault models require near optimal number of these operations.