Fault Models and Test Procedures for Flash Memory Disturbances
Journal of Electronic Testing: Theory and Applications
Electrical Model For Program Disturb Faults in Non-Volatile Memories
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A P1500-Compatible Programmable BIST Aapproach for the Test of Embedded Flash Memories
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash
Journal of Electronic Testing: Theory and Applications
An efficient fault detection algorithm for NAND flash memory
ACM SIGAPP Applied Computing Review
Write disturbance modeling and testing for MRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories
Journal of Electronic Testing: Theory and Applications
Modeling and testing of interference faults in the nano NAND flash memory
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Non Volatile Memories (NVMs) can undergo different types of disturbances. These disturbances are particular to the technology and the cell structure of the memory element. In this paper, we develop a coupling fault model that appropriately models disturbances in Flash memories that use floating gate transistor as their core memory element. We describe the behavior of faulty cells under different fault models and how their characteristics change under each model. We demonstrate the inappropriateness of conventional march algorithms for testing flash memories and present a procedure to derive Pseudo-algorithms that can be used in testing flash memories. In addition we present an efficient test that detects these disturbances under different fault models developed in this paper.