Modeling and testing of interference faults in the nano NAND flash memory

Authors:
Jin Zha;Xiaole Cui;Chung Len Lee
Affiliations:
Peking University, Guangdong Province, China;Peking University, Guangdong Province, China;Peking University, Guangdong Province, China
Venue:
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2012

Citing 4
Cited 0

Testing semiconductor memories: theory and practice

Testing semiconductor memories: theory and practice
Flash Memory Disturbances: Modeling and Test

VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
RAMSES-FT: A Fault Simulator for Flash Memory Testing and Diagnostics

VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Advance of the fabrication technology has enhanced the size and density for the NAND Flash memory but also brought new types of defects which need to be tested for the quality consideration. This work analyzes three types of physical defects for the deep nano-meter NAND Flash memory based on the circuit level simulation and proposes new categories of interference faults (IFs). Testing algorithm is also proposed to test the faults under the worst case condition. The algorithm, in addition to test IFs, can also detect the conventional address faults, disturbance faults and other RAM-like faults for the NAND Flash.