Electrical Model For Program Disturb Faults in Non-Volatile Memories
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Techniques for Disturb Fault Collapsing
Journal of Electronic Testing: Theory and Applications
An efficient fault detection algorithm for NAND flash memory
ACM SIGAPP Applied Computing Review
Write disturbance modeling and testing for MRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and testing of interference faults in the nano NAND flash memory
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we present a fault simulator for flash memory testing and diagnostics, called RAMSES-FT. The fault simulator is designed for easy inclusion of new fault models by adding their fault descriptors without modifying the simulation engine. The flash memory fault models are discussed, based on the failures defined in the IEEE 1005 Standard.Both the NOR-type and NAND-type flash memory architectures are covered. Our flash memory fault simulator uses a parallel simulation strategy to reduce the simulation time complexity from O(N3) to O(N2) where N is the number of cells. With the proposed scaling method for March tests, the simulation time complexity is further reduced to O(W2) where W is the word width of the memory. The fault simulator supports March algorithms as well as single memory operations, covering most of the flash memory tests. With RAMSES-FT, we have developed a diagnostic algorithm that can distinguish the target flash memory faults.