SRAM delay fault modeling and test algorithm development
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Automatic Generation of Diagnostic Memory Tests Based on Fault Decomposition and Output Tracing
IEEE Transactions on Computers
Raisin: Redundancy Analysis Algorithm Simulation
IEEE Design & Test
Write disturbance modeling and testing for MRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.04 |
The size and density of semiconductor memories is rapidly growing, making them increasingly harder to test. New fault models and test algorithms have been continuously proposed to cover defects and failures of modern memory chips and cores. However, software tool support for automating the memory test development procedure is still insufficient. For this purpose, we have developed a fault simulator (called RAMSES) and a test algorithm generator (called TAGS) for random-access memories (RAMs). In this paper, we present the algorithms and other details of RAMSES and TAGS and the experimental results of these tools on various memory architectures and configurations. We show that efficient test algorithms can be generated automatically for bit-oriented memories, word-oriented memories, and multiport memories, with 100% coverage of the given typical RAM faults