SRAM delay fault modeling and test algorithm development

Authors:
Rei-Fu Huang;Yan-Ting Lai;Yung-Fa Chou;Cheng-Wen Wu
Affiliations:
National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan
Venue:
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Year:
2004

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Abstract

With the advent of deep-submicron VLSI technologies, the working speed of SRAM circuits has grown to a level that at-speed testing of SRAM has become an important issue. In this paper, we present delay fault models for SRAM, i.e., the faults that affect the access time of the SRAM circuit. We also develop the test algorithm that detects these faults. The proposed SRAM delay-fault test algorithm has a complexity of Read/Write operations, where is the number of words and is the word count in a row.