Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Crosstalk Minimization in Three-Layer HVH Channel Routing
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs
Proceedings of the IEEE International Test Conference
Test generation in VLSI circuits for crosstalk noise
ITC '98 Proceedings of the 1998 IEEE International Test Conference
An Algorithmic Test Generation Method for Crosstalk Faults in Synchronous Sequential Circuits
ATS '97 Proceedings of the 6th Asian Test Symposium
Inductance Analysis of On-Chip Interconnects
EDTC '97 Proceedings of the 1997 European conference on Design and Test
2.3 Automatic Test Pattern Generation for Crosstalk Glitches in Digital Circuits
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Methods for Calculating Coupling Noise in Early Design: A Comparative Analysis
ICCD '98 Proceedings of the International Conference on Computer Design
Aggressor alignment for worst-case coupling noise
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Modeling and minimization of interconnect energy dissipation in nanometer technologies
Proceedings of the 38th annual Design Automation Conference
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Test of future system-on-chips
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
Noise Generation and Coupling Mechanisms in Deep-Submicron ICs
IEEE Design & Test
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
Journal of Electronic Testing: Theory and Applications
Analysis of Interconnect Crosstalk Defect Coverage of Test Sets
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
SRAM delay fault modeling and test algorithm development
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Extending JTAG for Testing Signal Integrity in SoCs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Using a Periodic Square Wave Test Signal to Detect Crosstalk Faults
IEEE Design & Test
Design, Synthesis, and Test of Networks on Chips
IEEE Design & Test
Evaluation of SEU and crosstalk effects in network-on-chip switches
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs
Journal of Electronic Testing: Theory and Applications
Crosstalk fault modeling in defective pair of interconnects
Integration, the VLSI Journal
Crosstalk- and SEU-Aware Networks on Chips
IEEE Design & Test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A new high-speed interconnect crosstalk fault model and compression for test space
WSEAS TRANSACTIONS on COMMUNICATIONS
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Test pattern generation for crosstalk fault of high-speed interconnect
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
A unified detection scheme for crosstalk effects in interconnection bus
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fault-tolerant NoC scheme using bidirectional channel
Proceedings of the 48th Design Automation Conference
Journal of Electronic Testing: Theory and Applications
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Journal of Electronic Testing: Theory and Applications
Modeling of crosstalk fault in defective interconnects
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Journal of Electronic Testing: Theory and Applications
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis
Journal of Electronic Testing: Theory and Applications
A fully parallel BIST-based method to test the crosstalk defects on the inter-switch links in NOC
Microelectronics Journal
Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy
Proceedings of the Conference on Design, Automation and Test in Europe
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Online traffic-aware fault detection for networks-on-chip
Journal of Parallel and Distributed Computing
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System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies [3,4], as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC.Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all physical level defects related to cross-coupling capacitance between the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.