Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Interconnect tuning strategies for high-performance ICs
Proceedings of the conference on Design, automation and test in Europe
VHDL: Analysis and Modeling of Digital Systems
VHDL: Analysis and Modeling of Digital Systems
ITC '98 Proceedings of the 1998 IEEE International Test Conference
2.2 Signal Integrity Problems in Deep Submicron Arising from Interconnects between Cores
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Instruction Randomization Self Test For Processor Cores
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Arithmetic built-in self-test for DSP cores
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Hi-index | 0.00 |
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for system-on-chips (SoC) based on embedded processors. It enables an on-chip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.