Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
Journal of Electronic Testing: Theory and Applications
Fault tolerant bus architecture for deep submicron based processors
ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
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For system-on-chips (SoC) using deep submicron (DSM) technologies, interconnects are becoming critical determinants for performance and reliability. Buses and long interconnects are susceptible to crosstalk defects and may lead to functional and timing failure. Hence, testing for crosstalk errors on interconnects and buses in a SoC has become critical. To facilitate development of new crosstalk test methodologies and to efficiently evaluate crosstalk defect coverage for existing tests, there is a need for efficient crosstalk defect coverage analysis techniques. In this paper, we present an efficient high-level crosstalk defect simulation methodology. By using a novel high-level DSM error model for the interconnects, together with HDL models for the cores, our methodology enables fast crosstalk defect simulation to be conducted at high level. We validate the high-level interconnect DSM error model by comparing its outputs with HSPICE simulation results. The fast and accurate high-level crosstalk defect simulation methodology will enable evaluation and exploration of new crosstalk test techniques, as well as existing tests, leading to the development of low-cost crosstalk test.