Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Electromigration reliability enhancement via bus activity distribution
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus encoding to prevent crosstalk delay
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Shielding effect of on-chip interconnect inductance
Proceedings of the 13th ACM Great Lakes symposium on VLSI
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Minimization of Crosstalk Noise, Delay and Power Using a Modi.ed Bus Invert Technique
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Frequency Domain Testing of General Purpose Processors at the Instruction Execution Level
DELTA '04 Proceedings of the Second IEEE International Workshop on Electronic Design, Test and Applications
High-speed architectures for parallel long BCH encoders
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Compact thermal modeling for temperature-aware design
Proceedings of the 41st annual Design Automation Conference
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Electromigration for microarchitects
ACM Computing Surveys (CSUR)
Enabling trusted scheduling in embedded systems
Proceedings of the 28th Annual Computer Security Applications Conference
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In the Deep Submicron era testing of processors is gaining prominence due to the effect of many analog faults. These faults have a direct impact on the signal integrity in interconnects. In deep submicron based processors electromigration poses a major challenge for interconnect reliability. This is of major concern in processor bus architectures. Though a lot of research has been focused on fault tolerance at the module level, no effective research has been carried out to evolve fault tolerant interconnect structures. Faults due to electromigration give rise to weak ones and zeros, thus affecting the signal integrity. This paper presents a fault tolerant scheme for electromigration which also leads to unification of detection and correction of crosstalk faults and stuck-at faults. In the scheme presented, the signal is rerouted through adjacent spare interconnects. The spare interconnect also acts as a shield against crosstalk under fault free system operation. Moreover, the entire testing process is carried out concurrently with the processor instruction execution. The hardware overhead is also insignificant compared to the overall device count in a deep submicron based processor. To the best of our knowledge this is the first time a fault tolerant scheme for bus architectures is being presented.