High-speed architectures for parallel long BCH encoders

Authors:
Xinmiao Zhang;Keshab K. Parhi
Affiliations:
University of Minnesota, Minneapolis, MN;University of Minnesota, Minneapolis, MN
Venue:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Year:
2004

Citing 2
Cited 3

Error control systems for digital communication and storage

Error control systems for digital communication and storage
A two-step computation of cyclic redundancy code CRC-32 for ATM networks

IBM Journal of Research and Development

Fault tolerant bus architecture for deep submicron based processors

ACM SIGARCH Computer Architecture News - Special issue: Workshop on architectural support for security and anti-virus (WASSA)
High-speed architectures for parallel long BCH encoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High speed VLSI architecture for general linear feedback shift register (LFSR) structures

Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers

Quantified Score

Hi-index	0.04

Visualization

Abstract

Long BCH codes are used as the outer error-correcting code in the second generation of Digital Video Broadcasting Standard from the European Telecommunications Standard Institute. These codes can achieve around 0.6dB additional coding gain over Reed-Solomon codes with similar codeword length and code rate in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. High-speed applications of BCH codes require parallel implementations of encoders. In addition, long BCH encoders suffer from the effect of large fanout. In this paper, novel architectures are proposed to reduce the achievable minimum clock period of long BCH encoders after the fanout bottleneck has been eliminated. For an (8191, 7684) BCH code, compared to the original 32-parallel BCH encoder architecture without fanout bottleneck, the proposed architectures can achieve a speedup of over 100%.