Error control systems for digital communication and storage
Error control systems for digital communication and storage
A two-step computation of cyclic redundancy code CRC-32 for ATM networks
IBM Journal of Research and Development
High-speed architectures for parallel long BCH encoders
Proceedings of the 14th ACM Great Lakes symposium on VLSI
CRT-based high-speed parallel architecture for long BCH encoding
IEEE Transactions on Circuits and Systems II: Express Briefs
VLSI implementation of BCH error correction for multilevel cell NAND flash memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Long Bose-Chaudhuri-Hocquenghen (BCH) codes are used as the outer error correcting codes in the second-generation Digital Video Broadcasting Standard from the European Telecommunications Standard Institute. These codes can achieve around 0.6-dB additional coding gain over Reed-Solomon codes with similar code rate and codeword length in long-haul optical communication systems. BCH encoders are conventionally implemented by a linear feedback shift register architecture. High-speed applications of BCH codes require parallel implementation of the encoders. In addition, long BCH encoders suffer from the effect of large fanout. In this paper, three novel architectures are proposed to reduce the achievable minimum clock period for long BCH encoders after the fanout bottleneck has been eliminated. For an (8191, 7684) BCH code, compared to the original 32-parallel BCH encoder architecture without fanout bottleneck, the proposed architectures can achieve a speedup of over 100 %.