High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ultra Folded High-Speed Architectures for Reed-Solomon Decoders
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
High-speed architectures for parallel long BCH encoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliability analysis and improvement for multi-level non-volatile memories with soft information
Proceedings of the 48th Design Automation Conference
Revisiting widely held SSD expectations and rethinking system-level implications
Proceedings of the ACM SIGMETRICS/international conference on Measurement and modeling of computer systems
Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling
Proceedings of the Conference on Design, Automation and Test in Europe
Product code schemes for error correction in MLC NAND flash memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Bit-error correction is crucial for realizing cost-effective and reliable NAND Flash-memory-based storage systems. In this paper, low-power and high-throughput error-correction circuits have been developed for multilevel cell (MLC) NAND Flash memories. The developed circuits employ the Bose-Chaudhuri-Hocquenghem code to correct multiple random bit errors. The error-correcting codes for them are designed based on the bit-error characteristics of MLC NAND Flash memories for solid-state drives. To trade the code rate, circuit complexity, and power consumption, three error-correcting architectures, named as whole-page, sector-pipelined, and multistrip ones, are proposed. The VLSI design applies both algorithmic and architectural-level optimizations that include parallel algorithm transformation, resource sharing, and time multiplexing. The chip area, power consumption, and throughput results for these three architectures are presented.