Error Correcting Strategy for High Speed and High Density Reliable Flash Memories
Journal of Electronic Testing: Theory and Applications
High-speed VLSI architecture for parallel Reed-Solomon decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
Design tradeoffs for SSD performance
ATC'08 USENIX 2008 Annual Technical Conference on Annual Technical Conference
An Adaptive-Rate Error Correction Scheme for NAND Flash Memory
VTS '09 Proceedings of the 2009 27th IEEE VLSI Test Symposium
Area-efficient Reed-Solomon decoder design for optical communications
IEEE Transactions on Circuits and Systems II: Express Briefs
Characterizing flash memory: anomalies, observations, and applications
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects
DFT '09 Proceedings of the 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Empirical evaluation of NAND flash memory performance
ACM SIGOPS Operating Systems Review
VLSI implementation of BCH error correction for multilevel cell NAND flash memory
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improving multi-level NAND flash memory storage reliability using concatenated BCH-TCM coding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Error control coding (ECC) is essential for correcting soft errors in Flash memories. In this paper we propose use of product code based schemes to support higher error correction capability. Specifically, we propose product codes which use Reed-Solomon (RS) codes along rows and Hamming codes along columns and have reduced hardware overhead. Simulation results show that product codes can achieve better performance compared to both Bose-Chaudhuri-Hocquenghem codes and plain RS codes with less area and low latency. We also propose a flexible product code based ECC scheme that migrates to a stronger ECC scheme when the numbers of errors due to increased program/erase cycles increases. While these schemes have slightly larger latency and require additional parity bit storage, they provide an easy mechanism to increase the lifetime of the Flash memory devices.