On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays
IEEE Transactions on Computers
Error control systems for digital communication and storage
Error control systems for digital communication and storage
Reed-Solomon Codes and Their Applications
Reed-Solomon Codes and Their Applications
Microprocessors: Fundamentals and Applications
Microprocessors: Fundamentals and Applications
An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRs
IEEE Transactions on Consumer Electronics
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Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEEE Transactions on Circuits and Systems II: Express Briefs
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Proceedings of the 4th International Conference on Uniquitous Information Management and Communication
Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications
Journal of Signal Processing Systems
Product code schemes for error correction in MLC NAND flash memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents high-speed parallel Reed-Solomon (RS) (255,239) decoder architecture using modified Euclidean algorithm for the high-speed multigigabit-per-second fiber optic systems. Pipelining and parallelizing allow inputs to be received at very high fiber-optic rates and outputs to be delivered at correspondingly high rates with minimum delay. Parallel processing architecture results in speed-ups of as much as or more than 10 Gb, since the maximum achievable clock frequency is generally bounded by the critical path of the modified Euclidean algorithm block. The parallel RS decoders have been designed and implemented with the 0.13-µm CMOS standard cell technology in a supply voltage of 1.1 V. It is suggested that a parallel RS decoder, which can keep up with optical transmission rates, i.e., 10 Gb/s and beyond, could be implemented. The proposed channel = 4 parallel RS decoder operates at a clock frequency of 770 MHz and has a data processing rate of 26.6 Gb/s.