A high-speed two-cell BCH decoder for error correcting in MLC NOR flash memories

  • Authors:

  • Wang Xueqiang;Pan Liyang;Wu Dong;Hu Chaohong;Zhou Runde

  • Affiliations:

  • Institute of Microelectronics, Tsinghua University, Beijing, China;Institute of Microelectronics and Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China;Institute of Microelectronics and Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China;Intel Technology Development Co., Ltd., Shanghai, China;Institute of Microelectronics and Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing, China

  • Venue:
  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • Year:
  • 2009

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Abstract

An on-chip high-speed two-cell Bose-Chaudhuri-Hocquenghen (BCH) decoder for error correction in a multilevel-cell (MLC) NOR flash memory is presented. To satisfy the reliability requirements, a double-error-correcting (DEC) BCH code is required in NOR flash memories with the process shrinking beyond 45 nm. A novel fast-decoding algorithm is developed to speed up the BCH decoding process using iteration-free solutions and division-free transformations in finite fields. As a result, the decoding latency is significantly reduced by 80%. Furthermore, a novel architecture of a two-cell decoder that is suitable for an MLC flash memory is proposed to obtain a good time-area tradeoff. Experimental results show that the latency of the proposed two-cell BCH decoder is only 7.5 ns, which satisfies the fast-access-time requirements of NOR flash memories.