Wireless Communications: Principles and Practice
Wireless Communications: Principles and Practice
Reed-Solomon Codes and Their Applications
Reed-Solomon Codes and Their Applications
High-speed VLSI architecture for parallel Reed-Solomon decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture for decoding adaptive Reed-Solomon codes with variable block length
IEEE Transactions on Consumer Electronics
Adaptation techniques in wireless packet data services
IEEE Communications Magazine
A field programmable gate array media player for realmedia files
Journal of Computing Sciences in Colleges
Application development on hybrid systems
Proceedings of the 2007 ACM/IEEE conference on Supercomputing
Visions for application development on hybrid computing systems
Parallel Computing
Sorting on architecturally diverse computer systems
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications
Hardware vs. software implementations for calculating roots of polynomials
Journal of Computing Sciences in Colleges
| Hi-index | 0.00 |
The development of Reed-Solomon (RS) codes has allowed for improved data transmission over a variety of communication media. Although Reed-Solomon decoding provides a powerful defense against burst data errors, the significant circuit area and power consumption of customized RS decoder hardware can be limiting for embedded computing environments. To support enhanced performance decoding with minimal power consumption, a dynamically-reconfigurable FPGA-based Reed-Solomon decoder has been developed. Our errors-and-erasures decoding system uses multiple erasure blocks to identify the location of likely corrupted data and multiple decoders to attempt error correction. The RS decoder design is implemented in reconfigurable hardware to leverage architectural parallelism and specialization. Run-time dynamic reconfiguration of the decoding system is used in response to variations in channel conditions to support the fastest possible data rate while, as a secondary metric, minimizing decoder power consumption. Algorithm parameters for the decoding system have been determined via simulation and the design has been implemented in Altera Stratix FPGAs. Through experimentation using an Altera 1S40 Stratix FPGA, we show that dynamic reconfiguration can result in an 14% performance improvement versus a non-reconfigurable decoder implementation. Comparisons with a Pentium IV microprocessor illustrate five orders of magnitude performance improvement.