Error-control coding for computer systems
Error-control coding for computer systems
High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-speed VLSI architecture for parallel Reed-Solomon decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A VLSI Design of a Pipeline Reed-Solomon Decoder
IEEE Transactions on Computers
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
New degree computationless modified euclid algorithm and architecture for reed-solomon decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes a high-speed and area-efficient three-parallel RS decoder using the simplified degree computationless modified Euclid (S-DCME) algorithm for the key equation solver (KES) block. To achieve high throughput rate, three inner signals such as syndrome, error locator and error value polynomials are computed in parallel. In addition, the key equation is solved by using the S-DCME algorithm to reduce hardware complexity. To resolve the problem caused by using S-DCME to KES block of parallel architecture, we assign an inner reset signal to settle the problem. The proposed KES block can reduce about 80% of hardware complexity. In addition, the proposed RS architecture has approximately 25% shorter latency compared with conventional parallel RS architectures.