IEEE Transactions on Computers
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder
IEICE - Transactions on Information and Systems
Area-efficient Reed-Solomon decoder design for optical communications
IEEE Transactions on Circuits and Systems II: Express Briefs
Modified Euclidean algorithms for decoding Reed-Solomon codes
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 2
Reed-Solomon codec for a reconfigurable baseband processing platform
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
High-speed architecture for three-parallel Reed-Solomon decoder using S-DCME
Proceedings of the 4th International Conference on Uniquitous Information Management and Communication
Three-Parallel Reed-Solomon Decoder Using S-DCME for High-Speed Communications
Journal of Signal Processing Systems
Implementation of adaptive reed-solomon decoder for context-aware mobile computing device
KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
New Cost-Effective Simplified Euclid's Algorithm for Reed-Solomon Decoders
Journal of Signal Processing Systems
Hi-index | 14.98 |
A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a (15,9) RS code.