Reed-Solomon codec for a reconfigurable baseband processing platform

Authors:
Qingqing Yang;Xiaofang Zhou;Gerald E. Sobelman
Affiliations:
State Key Laboratory of ASIC & System, Fudan University, Shanghai, China;State Key Laboratory of ASIC & System, Fudan University, Shanghai, China;Dept. of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN
Venue:
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
Year:
2009

Citing 5
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High-speed architectures for Reed-Solomon decoders

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A VLSI Design of a Pipeline Reed-Solomon Decoder

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Multi-symbol-sliced dynamically reconfigurable reed-solomon decoder design based on unified finite-field processing element

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Abstract

This paper presents the VLSI design of a multi-mode Reed-Solomon codec. Our decoder design is based on the modified Euclidean (ME) algorithm and shares hardware between the ME algorithm and the computation part of the Chien search. With its ability to support a variety of RS(n, k, t) code parameters (0≤n≤255), (0≤t≤8) as well as different finite fields GF(2m), (3≤m≤8), this RS codec design is suitable for use in a reconfigurable baseband processing platform. Synthesis results indicate that this codec operates at a maximum frequency of 177 MHz and has a peak data processing rate of 1416 Mbps.