On the VLSI Design of a Pipeline Reed-Solomon Decoder Using Systolic Arrays
IEEE Transactions on Computers
Error-control coding for computer systems
Error-control coding for computer systems
Error control systems for digital communication and storage
Error control systems for digital communication and storage
High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Channel Coding for Telecommunications
Channel Coding for Telecommunications
Error-Control Coding for Data Networks
Error-Control Coding for Data Networks
Reed-Solomon Codes and Their Applications
Reed-Solomon Codes and Their Applications
IEEE Transactions on Circuits and Systems for Video Technology
Bit manipulation accelerator for communication systems digital signal processor
EURASIP Journal on Applied Signal Processing
A reconfigurable FEC system based on Reed-Solomon codec for DVB and 802.16 network
WSEAS Transactions on Circuits and Systems
Reed-Solomon codec for a reconfigurable baseband processing platform
WiCOM'09 Proceedings of the 5th International Conference on Wireless communications, networking and mobile computing
A reconfigurable processor for forward error correction
ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents new application-specific digital signal processor (ASDSP) instructions and their hardware accelerator to efficiently implement Reed-Solomon (RS) encoding and decoding, which is one of the most widely used forward error control (FEC) algorithms. The proposed ASDSP architecture can implement various programmable primitive polynomials, and thus, hardwired RS codecs can be replaced. The new instructions and their hardware accelerator perform Galois field (GF) operations using the proposed GF multiplier and adder. Therefore, the proposed digital signal processor (DSP) architecture can significantly reduce the number of clock cycles compared with existing DSP chips. The proposed GF multiplier was implemented using the Faraday 0.25 µm standard cell library and it can perform RS decoding at a rate up to 228.1 Mbps at 130 MHz.