A VLSI Design of a Pipelining and Area-Efficient Reed-Solomon Decoder

  • Authors:

  • Wei-min Wang;Du-yan Bi;Xing-min Du;Lin-hua Ma

  • Affiliations:

  • -;-;-;-

  • Venue:
  • IEICE - Transactions on Information and Systems
  • Year:
  • 2007

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Abstract

A novel high-speed and area-efficient Reed-Solomon decoder is proposed, which employs pipelining architecture of minimized modified Euclid (ME) algorithm. The logic synthesis and simulation results of its VLSI implementation show that it not only can operate at a higher clock frequency, but also consumes fewer hardware resources.