High-speed architectures for Reed-Solomon decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of VLSI Signal Processing Systems
High-speed VLSI architecture for parallel Reed-Solomon decoder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI architecture of modified Euclidean algorithm for Reed-Solomon code
Information Sciences: an International Journal
A Comparative Evaluation of Designs for Reliable Memory Systems
Journal of Electronic Testing: Theory and Applications
Modified Euclidean algorithms for decoding Reed-Solomon codes
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 2
| Hi-index | 0.43 |
A new flexible and area-efficient VLSI architecture of a Reed-Solomon product-code decoder/encoder has been developed for digital VCRs. The new architecture of the decoder/encoder targeted to reduce the circuit size and decoding latency has the following three features. First, a high area-efficiency has been achieved by sharing a functional block for encoding, modified syndrome computation, and erasure locator polynomial evaluation. Second, the circuit size and decoding latency has been reduced by using a new architecture to implement the modified Euclid's algorithm. Third, by doubling the internal clock speed (from 18 MHz to 36 MHz), the decoding latency and hence the memory size can be reduced. The decoder/encoder designed by using the proposed method uses a reduced number of gates, by about 30%, than the one based on the conventional architectures