A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm

  • Authors:

  • Huai-Yi Hsu;Sheng-Feng Wang;An-Yeu (Andy) Wu

  • Affiliations:

  • Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, Taiwan, Republic of China;Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, Republic of China;Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei 106, Taiwan, Republic of China

  • Venue:
  • Journal of VLSI Signal Processing Systems
  • Year:
  • 2003

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Abstract

Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Among various Reed-Solomon decoding algorithms, the Peterson-Gorenstein-Zierler (PGZ) algorithm in general has the least computational complexity for small t values. However, unlike the iterative approaches (e.g., Berlekamp-Massey and Euclidean algorithms), it will encounter divided-by-zero problems in solving multiple t values. In this paper, we propose a multi-mode hardware architecture for error numbers ranging from zero to three. We first propose a cost-down technique to reduce the hardware complexity of a t = 3 decoder. A Finite-field Inversion (FFI) elimination scheme is also proposed in our PGZ kernel. Next, we perform an algorithmic-level derivation to identify the configurable feature of our design. With those manipulations, we are able to perform multi-mode RS decoding in one unified VLSI architecture with very simple control scheme. The very low cost and simple data-path make our design a good choice in small-footprint embedded VLSI systems such as Error Control Coding (ECC) in memory/storage systems.