Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Terrestrial cosmic ray intensities
IBM Journal of Research and Development
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Efficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
SRAM Test Using On-Chip Dynamic Power Supply Current Sensor
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
ISMVL '02 Proceedings of the 32nd International Symposium on Multiple-Valued Logic
IDDQ Testing for Submicron CMOS IC Technology Qualification
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
Markov Models of Fault-Tolerant Memory Systems under SEU
MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
An area-efficient VLSI architecture of a Reed-Solomon decoder/encoder for digital VCRs
IEEE Transactions on Consumer Electronics
Analysis of Errors and Erasures in Parity Sharing RS Codecs
IEEE Transactions on Computers
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This paper addresses the design of storage systems for operation under critical environmental conditions. For these applications, these systems should have low latency time in access, high performance in throughput and high storage capabilities; therefore, they must be assembled using highly reliable components, while allowing flexibility in design. Commercial Off The Shelf (COTS) components have often been used. A COTS-based architecture is analyzed in this paper; the proposed architecture uses design-level techniques (such as error detection/correction codes and scrubbing) to make commercially available Dynamic Random Access Memory (DRAM) chips tolerant to faults. This paper provides a complete and novel analysis of engineering alternatives which arise in the design of a highly reliable memory system based on Reed Solomon coding. A comparative analysis of methods for permanent fault detection is provided; moreover using a Markovian characterization, different functional arrangements (based on code and scrubbing frequency) are investigated and evaluated.