A Super-Serial Galois Fields Multiplier for FPGAs and its Application to Public-Key Algorithms
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Hardware architectures for public key cryptography
Integration, the VLSI Journal
A Comparative Evaluation of Designs for Reliable Memory Systems
Journal of Electronic Testing: Theory and Applications
Vectorization of Reed solomon decoding and mapping on the EVP
Proceedings of the conference on Design, automation and test in Europe
Efficient hardware multiplicative inverters
ICISC'02 Proceedings of the 5th international conference on Information security and cryptology
TWISTERπ – a framework for secure and fast hash functions
International Journal of Applied Cryptography
Implementation of adaptive reed-solomon decoder for context-aware mobile computing device
KES'05 Proceedings of the 9th international conference on Knowledge-Based Intelligent Information and Engineering Systems - Volume Part I
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Reed-Solomon (RS) error correction codes are being widely used in modern communication systems such as compact disk players or satellite communication links. RS codes rely on arithmetic in finite, or Galois fields. The specific field GF(2/sup 8/) is of central importance for many practical systems. The most costly, and thus most critical, elementary operations in RS decoders are multiplication and inversion in Galois fields. Although there have been considerable efforts in the area of Galois field arithmetic architectures, there appears to be very little reported work for Galois field arithmetic for reconfigurable hardware. This contribution provides a systematic comparison of two promising arithmetic architecture classes. The first one is based on a standard base representation, and the second one is based on composite fields. For both classes a multiplier and an inverter for GF(2/sup 8/) are described and theoretical gate counts are provided. Using a design entry based on a VHDL description, each architecture is mapped to a popular FPGA and EPLD device. For each mapping an area and a speed optimization was performed. Absolute values with respect to logic cell counts and critical path simulations are provided. The results show that the composite field architectures can have great advantages on both types of reconfigurable platforms. In particular it is found that composite field multipliers can be more than twice as fast as polynomial base multipliers on FPGAs.