Vectorization of Reed solomon decoding and mapping on the EVP

Authors:
Akash Kumar;Kees van Berkel
Affiliations:
Eindhoven University of Technology, Eindhoven, The Netherlands;Eindhoven University of Technology, Eindhoven, The Netherlands and NXP Semiconductors, Eindhoven, The Netherlands
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2008

Citing 4
Cited 0

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Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware

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A fast parallel reed-solomon decoder on a reconfigurable architecture

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Vector processing as an enabler for software-defined radio in handheld devices

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Abstract

Reed Solomon (RS) codes are used in a variety of (wireless) communication systems. Although commonly implemented in dedicated hardware, this paper explores the mapping of high-throughput RS decoding on vector DSPs. The four modules of such a decoder, viz. Syndrome Computation, Key Equation Solver, Chien Search, and Forney pose different vectorization challenges. Their vectorizations are explained in detail, including optimizations specific for Embedded Vector Processor (EVP). For RS (255, 239), this solution is benchmarked vs published implementations, and scalability up to vector size 64 is explored. The best and the worst case throughput of our implementation is 8 times and 2 times higher respectively than other architectures.