A parallel architecture for the self-sorting FFT algorithm
Journal of Parallel and Distributed Computing
DSP Processor Fundamentals: Architectures and Features
DSP Processor Fundamentals: Architectures and Features
The TigerSHARC DSP Architecture
IEEE Micro
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
A software-defined communications baseband design
IEEE Communications Magazine
Design and implementation of an all-CMOS 802.11a wireless LAN chipset
IEEE Communications Magazine
Evolution of spectrum-agile cognitive radios: first wireless internet standard and beyond
WICON '06 Proceedings of the 2nd annual international workshop on Wireless internet
The sandbridge SB3011 platform
EURASIP Journal on Embedded Systems
Scheduling multiple independent hard-real-time jobs on a heterogeneous multiprocessor
EMSOFT '07 Proceedings of the 7th ACM & IEEE international conference on Embedded software
Vectorization of Reed solomon decoding and mapping on the EVP
Proceedings of the conference on Design, automation and test in Europe
Retargetable code optimization for predicated execution
Proceedings of the conference on Design, automation and test in Europe
From SODA to scotch: The evolution of a wireless baseband processor
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
AnySP: anytime anywhere anyway signal processing
Proceedings of the 36th annual international symposium on Computer architecture
Modeling Scalable SIMD DSPs in LISA
SAMOS '09 Proceedings of the 9th International Workshop on Embedded Computer Systems: Architectures, Modeling, and Simulation
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
A DSP architecture optimized for wireless baseband
SOC'09 Proceedings of the 11th international conference on System-on-chip
Trends in low power handset software defined radio
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Area efficient fully programmable baseband processors
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
A system level algorithmic approach toward energy-aware SDR baseband implementations
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
Diet SODA: a power-efficient processor for digital cameras
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors
Journal of Signal Processing Systems
A low cost multi-standard near-optimal soft-output sphere decoder: algorithm and architecture
Proceedings of the Conference on Design, Automation and Test in Europe
Domain specific architecture for next generation wireless communication
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Resource recycling: putting idle resources to work on a composable accelerator
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
CASES '10 Proceedings of the 2010 international conference on Compilers, architectures and synthesis for embedded systems
A programmable, scalable-throughput interleaver
EURASIP Journal on Wireless Communications and Networking
A low-power DSP for wireless communications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy Aware Signal Processing for Software Defined Radio Baseband Implementation
Journal of Signal Processing Systems
Analyzing the Next Generation Software Defined Radio for Future Architectures
Journal of Signal Processing Systems
Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
Journal of Signal Processing Systems
Multi-radio coexistence and collaboration on an SDR platform
Analog Integrated Circuits and Signal Processing
Instructions and hardware designs for accelerating SNOW 3G on a software-defined radio platform
Analog Integrated Circuits and Signal Processing
SIMD defragmenter: efficient ILP realization on data-parallel architectures
ASPLOS XVII Proceedings of the seventeenth international conference on Architectural Support for Programming Languages and Operating Systems
Throughput-constrained voltage and frequency scaling for real-time heterogeneous multiprocessors
Proceedings of the 28th Annual ACM Symposium on Applied Computing
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
A 100 GOPS ASP based baseband processor for wireless communication
Proceedings of the Conference on Design, Automation and Test in Europe
A complexity adaptive channel estimator for low power
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Numerical Aspects of MIMO OFDM PHY Layer Applications on SDR Platforms
Journal of Signal Processing Systems
Power Efficient SDR Implementation of IEEE 802.11a/p Physical Layer
Journal of Signal Processing Systems
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A major challenge of software-defined radio (SDR) is to realize many giga operations per second of flexible baseband processing within a power budget of only a few hundred mW. A heterogeneous hardware architecture with the programmable vector processor EVP as key component can support WLAN, UMTS, and other standards. A detailed rationale for the EVP architecture, based on the analysis of a number of key algorithms, as well as implementation and benchmarking results are described.