Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
Vector processing as an enabler for software-defined radio in handheld devices
EURASIP Journal on Applied Signal Processing
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing near-ML MIMO detector for SDR baseband on parallel programmable architectures
Proceedings of the conference on Design, automation and test in Europe
A coarse-grained array based baseband processor for 100Mbps+ software defined radio
Proceedings of the conference on Design, automation and test in Europe
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
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Emerging SDR baseband platforms are usually based on multiple DLP+ILP processors with massive parallelism [10]. Although these platforms would theoretically enable advanced SDR signal processing, existing work implemented basic systems and simple algorithms. Importantly, MIMO is not fully supported in most implementations [7][9][11]. [1] implemented MIMO but with a simple linear detector. Our work explores the feasibility for SDR implementations of soft-output ML MIMO detectors, which brings 6--12 dB SNR gains when compared to popular linear detectors. Although soft-output ML MIMO detectors are considered to be challenging even for ASICs [3][4], we combine architecture-friendly algorithms, application specific instructions, code transformations and ILP/DLP explorations to make SDR implementations feasible. In our work, a 2x4 ADRES based ASIP with 16-way SIMD can deliver 193Mbps for 2x2 64QAM, and 368Mbps for 2x2 16QAM transmissions. To the best of our knowledge, this is the first work exploring SDR based soft-output ML MIMO detectors.