Architecture Exploration for a Reconfigurable Architecture Template

Authors:
Bingfeng Mei;Andy Lambrechts;Diederik Verkest;Jean-Yves Mignolet;Rudy Lauwereins
Affiliations:
IMEC and Katholieke Universiteit Leuven;IMEC and Katholieke Universiteit Leuven;IMEC, Katholieke Universiteit Leuven, and Vrije Universiteit Brussel;IMEC;IMEC and Katholieke Universiteit Leuven
Venue:
IEEE Design & Test
Year:
2005

Citing 9
Cited 36

MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems

MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications

IEEE Transactions on Computers
A decade of reconfigurable computing: a visionary retrospective

Proceedings of the conference on Design, automation and test in Europe
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System

Journal of VLSI Signal Processing Systems
PipeRench: A Reconfigurable Architecture and Compiler

Computer
Mapping Applications onto Reconfigurable Kress Arrays

FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
RaPiD - Reconfigurable Pipelined Datapath

FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures

Proceedings of the conference on Design, automation and test in Europe - Volume 1
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1

Area and delay estimation for FPGA implementation of coarse-grained reconfigurable architectures

Proceedings of the 2006 ACM SIGPLAN/SIGBED conference on Language, compilers, and tool support for embedded systems
Reducing idle mode power in software defined radio terminals

Proceedings of the 2006 international symposium on Low power electronics and design
Compiler assisted architectural exploration for coarse grained reconfigurable arrays

Proceedings of the 17th ACM Great Lakes symposium on VLSI
Design space exploration of an optimized compiler approach for a generic reconfigurable array architecture

The Journal of Supercomputing
A unified evaluation framework for coarse grained reconfigurable array architectures

Proceedings of the 4th international conference on Computing frontiers
Design space exploration of partially re-configurable embedded processors

Proceedings of the conference on Design, automation and test in Europe
An energy-efficient reconfigurable baseband processor for wireless communications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Increasing data-bandwidth to instruction-set extensions through register clustering

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Modeling and simulation of parallel adaptive divide-and-conquer algorithms

The Journal of Supercomputing
Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors

ACM Transactions on Embedded Computing Systems (TECS)
An automatic scratch pad memory management tool and MPEG-4 encoder case study

Proceedings of the 45th annual Design Automation Conference
High-level modelling and exploration of coarse-grained re-configurable architectures

Proceedings of the conference on Design, automation and test in Europe
Embedded DSP Processor Design: Application Specific Instruction Set Processors

Embedded DSP Processor Design: Application Specific Instruction Set Processors
A framework for low energy data management in reconfigurable multi-context architectures

Journal of Systems Architecture: the EUROMICRO Journal
A design flow for architecture exploration and implementation of partially reconfigurable processors

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor Arrays

IEICE - Transactions on Information and Systems
On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks

ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Generic multiphase software pipelined partial FFT on instruction level parallel architectures

IEEE Transactions on Signal Processing
Compiling for reconfigurable computing: A survey

ACM Computing Surveys (CSUR)
Modeling of interconnection networks in massively parallel processor architectures

ARCS'07 Proceedings of the 20th international conference on Architecture of computing systems
Architectural exploration of the ADRES coarse-grained reconfigurable array

ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Architecture enhancements for the ADRES coarse-grained reconfigurable array

HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Runtime Reconfiguration of Multiprocessors Based on Compile-Time Analysis

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors

Proceedings of the Conference on Design, Automation and Test in Europe
Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach

IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Energy Aware Signal Processing for Software Defined Radio Baseband Implementation

Journal of Signal Processing Systems
Exploiting the distributed foreground memory in coarse grain reconfigurable arrays for reducing the memory bottleneck in DSP applications

SSIP'05 Proceedings of the 5th WSEAS international conference on Signal, speech and image processing
Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors

Journal of Signal Processing Systems
Test compression for dynamically reconfigurable processors

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Function inlining and loop unrolling for loop acceleration in reconfigurable processors

Proceedings of the 2012 international conference on Compilers, architectures and synthesis for embedded systems
Analysis of Inner-Loop Mapping onto Coarse-Grained Reconfigurable Architectures Using Hybrid Particle Swarm Optimization

International Journal of Organizational and Collective Intelligence
High-level design space and flexibility exploration for adaptive, energy-efficient WCDMA channel estimation architectures

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
Thermal-aware datapath merging for coarse-grained reconfigurable processors

Proceedings of the Conference on Design, Automation and Test in Europe
Architecture customization of on-chip reconfigurable accelerators

ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Ingredients of adaptability: a survey of reconfigurable processors

VLSI Design
Design of a coarse-grained reconfigurable architecture with floating-point support and comparative study

Integration, the VLSI Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

The vast design space of coarse-grained reconfigurable architectures complicates the design of optimized processors. However, a flexible architecture template and a retargetable simulator and compiler enable systematic architecture exploration that can lead to more efficient domain-specific architecture designs.