Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
Customizable Embedded Processors: Design Technologies and Applications
Customizable Embedded Processors: Design Technologies and Applications
Building ASIPs: The Mescal Methodology
Building ASIPs: The Mescal Methodology
Space-Time Wireless Systems: From Array Processing to MIMO Communications
Space-Time Wireless Systems: From Array Processing to MIMO Communications
Low power soft-output signal detector design for wireless MIMO communication systems
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Vector processing as an enabler for software-defined radio in handheld devices
EURASIP Journal on Applied Signal Processing
Relaxed K-best MIMO signal detector design and VLSI implementation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimizing near-ML MIMO detector for SDR baseband on parallel programmable architectures
Proceedings of the conference on Design, automation and test in Europe
A coarse-grained array based baseband processor for 100Mbps+ software defined radio
Proceedings of the conference on Design, automation and test in Europe
Implementation of a 2 × 2 MIMO-OFDM receiver on an application specific processor
Microelectronics Journal
Novel energy-efficient scalable soft-output SSFE MIMO detector architectures
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
Reconfigurable real-time MIMO detector on GPU
Asilomar'09 Proceedings of the 43rd Asilomar conference on Signals, systems and computers
ASIP-based flexible MMSE-IC linear equalizer for MIMO turbo-equalization applications
Proceedings of the Conference on Design, Automation and Test in Europe
Implementation of a High-Speed MIMO Soft-Output Symbol Detector for Software Defined Radio
Journal of Signal Processing Systems
Algorithm and implementation of the K-best sphere decoding for MIMO detection
IEEE Journal on Selected Areas in Communications
Area-Efficient Antenna-Scalable MIMO Detector for K-best Sphere Decoding
Journal of Signal Processing Systems
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Emerging Software Defined Radio (SDR) baseband platforms are based on multiple processors with massive parallelism. Although the computational power of these platforms would theoretically enable SDR solutions with advanced wireless signal processing, existing work implements still rather basic algorithms. For instance, current Multiple-Input Multiple-Output (MIMO) detector implementations are typically based on simple linear hard-output and not on advanced near-Maximum Likelihood (ML) soft-output detection. However, only the latter enables to exploit the full potential of MIMO technology. In this work, we explore the feasibility of advanced soft-output near-ML MIMO detectors on massive parallel processors. Although such detectors are considered to be very challenging due to their high computational complexity, we combine architecture-friendly algorithm design, application specific instructions and instruction-level/data-level parallelism explorations to make SDR solutions feasible. We show that, by applying the proposed combination of techniques, it is possible to obtain SDR implementations which can deliver data rates that are sufficient for future wireless systems. For example, a 2 脳 4 Coarse Grain Array (CGA) processor with 16-way Single Instruction Multiple Data (SIMD) can deliver 192/368 Mbps throughput for 2 脳 2 64/16-QAM transmissions. Finally, we estimate the area and power consumption of the programmable solution and compare it against a traditional Application Specific Integrated Circuit (ASIC) approach. This enables us to draw conclusions from the cost perspective.