Implementation of a 2 × 2 MIMO-OFDM receiver on an application specific processor

Authors:
Stefan Eberli;Andreas Burg;Wolfgang Fichtner
Affiliations:
Integrated Systems Laboratory, ETH Zentrum, ETZ J81, Gloriastrasse 35, CH-8092 Zurich, Switzerland;Integrated Systems Laboratory, ETH Zentrum, ETZ J81, Gloriastrasse 35, CH-8092 Zurich, Switzerland;Integrated Systems Laboratory, ETH Zentrum, ETZ J81, Gloriastrasse 35, CH-8092 Zurich, Switzerland
Venue:
Microelectronics Journal
Year:
2009

Citing 6
Cited 1

Computer arithmetic: algorithms and hardware designs

Computer arithmetic: algorithms and hardware designs
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture

IEEE Transactions on Computers
Software-Defined Radio Prospects for Multistandard Mobile Phones

Computer
Code Compressor and Decompressor for Ultra Large Instruction Width Coarse-Grain Reconfigurable Systems

FCCM '07 Proceedings of the 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
A coarse-grained array based baseband processor for 100Mbps+ software defined radio

Proceedings of the conference on Design, automation and test in Europe
The next generation challenge for software defined radio

SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation

Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors

Journal of Signal Processing Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes the implementation of the hard computational kernels required for the baseband (BB) processing of a 2x2 multiple-input multiple-output (MIMO)-OFDM receiver on a design-framework for application specific processors. The employed low-complexity BB algorithms are described and their computational complexity is derived. The receiver is split into two parts which are mapped onto two application specific processors, each tailored to the computational needs of the associated digital signal processing kernels. The first processor performs the per stream MIMO-OFDM processing. The second processor handles the MIMO detection. Finally, the 0.18@mm 1P/6M CMOS technology layout of both fabricated application specific processors is presented. Real-time BB processing is possible on these engines running at a clock frequency of 250MHz.