IEEE Transactions on Computers
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
SODA: A Low-power Architecture For Software Radio
Proceedings of the 33rd annual international symposium on Computer Architecture
A software-defined communications baseband design
IEEE Communications Magazine
A Communication and configuration controller for NoC based reconfigurable data flow architecture
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Implementation of a 2 × 2 MIMO-OFDM receiver on an application specific processor
Microelectronics Journal
An Efficient Memory Organization for High-ILP Inner Modem Baseband SDR Processors
Journal of Signal Processing Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Energy Aware Signal Processing for Software Defined Radio Baseband Implementation
Journal of Signal Processing Systems
Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors
Journal of Signal Processing Systems
ACM Transactions on Embedded Computing Systems (TECS)
System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor
International Journal of Embedded and Real-Time Communication Systems
Tomahawk: Parallelism and heterogeneity in communications signal processing MPSoCs
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
Power Efficient SDR Implementation of IEEE 802.11a/p Physical Layer
Journal of Signal Processing Systems
Hi-index | 0.00 |
The Software-Defined Radio (SDR) concept aims to enabling cost-effective multi-mode baseband solutions for wireless terminals. However, the growing complexity of new communication standards applying, e.g., multi-antenna transmission techniques, together with the reduced energy budget, is challenging SDR architectures. Coarse-Grained Array (CGA) processors are strong candidates to undertake both high performance and low power. The design of a candidate hybrid CGA-SIMD processor for an SDR baseband platform is presented. The processor, designed in TSMC 90G process according to a dual-VT standard-cells flow, achieves a clock frequency of 400MHz in worst case conditions and consumes maximally 310mW active and 25mW leakage power (typical conditions) when delivering up to 25,6GOPS (16-bit). The mapping of a 20MHz 2x2 MIMO-OFDM transmit and receive baseband functionality is detailed as an application case study, achieving 100Mbps+ throughput with an average consumption of 220mW.