Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling

Authors:
Bingfeng Mei;Serge Vernalde;Diederik Verkest;Hugo De Man;Rudy Lauwereins
Affiliations:
IMEC vzw and Katholic Universiteit Leuven;IMEC vzw;IMEC vzw and Vrije Universiteit Brussel;IMEC vzw and Katholic Universiteit Leuven;IMEC vzw and Katholic Universiteit Leuven
Venue:
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Year:
2003

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Abstract

Coarse-grained reconfigurable architectures have become increasingly important in recent years. Automatic design or compilation tools are essential to their success. In this paper, we present a modulo scheduling algorithm to exploit loop-level parallelism for coarse-grained reconfigurable architectures. This algorithm is a key part of our Dynamically Reconfigurable Embedded Systems Compiler (DRESC). It is capable of solving placement, scheduling and routing of operations simultaneously in a modulo-constrained 3D space and uses an abstract architecture representation to model a wide class of coarse-grained architectures. The experimental results show high performance and efficient resource utilization on tested kernels.