MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Proceedings of the conference on Design, automation and test in Europe
High Performance Compilers for Parallel Computing
High Performance Compilers for Parallel Computing
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
Instruction-Level Parallelism for Reconfigurable Computing
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Specifying and Compiling Applications for RaPiD
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Datapath merging and interconnection sharing for reconfigurable architectures
Proceedings of the 15th international symposium on System Synthesis
Compilation Approach for Coarse-Grained Reconfigurable Architectures
IEEE Design & Test
The design of dynamically reconfigurable datapath coprocessors
ACM Transactions on Embedded Computing Systems (TECS)
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices
IEEE Transactions on Parallel and Distributed Systems
Storage assignment during high-level synthesis for configurable architectures
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reducing power while increasing performance with supercisc
ACM Transactions on Embedded Computing Systems (TECS)
Automatic Design of Area-Efficient Configurable ASIC Cores
IEEE Transactions on Computers
A design scheme for a reconfigurable accelerator implemented by single-flux quantum circuits
Journal of Systems Architecture: the EUROMICRO Journal
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Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance applications [12]. The volume required to amortize these high costs has been increasing, making it increasingly expensive to afford ASIC solutions for medium volume products. This has led to designers seeking programmable solutions of varying sorts using these so-called programmable platforms. These programmable platforms span a large range from bit-level programmable Field Programmable Gate Arrays (FPGAs), to word-level programmable application-specific, and in some cases even general-purpose processors. The programmability comes with a power and performance overhead. Attempts to reduce this overhead typically involve making some core hardwired ASIC like logic blocks accessible to the programmable elements. This paper presents one such hybrid solution in this space - a relatively simple processor with a dynamically reconfigurable datapath acting as an accelerating co-processor. This datapath consists of hardwired function units and reconfigurable interconnect. We present a methodology for the design of these solutions and illustrate it with two complete case studies: an MPEG 2 coder, and a GSM coder, to show how significant speedups can be obtained using relatively little hardware. The co-processor can be viewed as a VLIW processor with a single instruction per kernel loop. We compare the efficiency of exploiting the operation level parallelism using classic VLIW processors and this proposed class of dynamically configurable co-processors. This work is part of the MESCAL project, which is geared towards developing design environments for the development of application specific platforms.